Review Problems for CS 30200 / ECE 46810 Exam 2 Spring 2015 Version 1.0. (In case I need to modify something.) The exam is over Chapters 13, 15, 16, 18, 19, 20, and 21 from the textbook. http://pages.cs.wisc.edu/~remzi/OSTEP/ http://pages.cs.wisc.edu/~remzi/OSTEP/vm-intro.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-mechanism.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-paging.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-tlbs.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-beyondphys.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-beyondphys-policy.pdf 1. Explain two differences between virtual addresses and physical addresses. 2. In a base-and-bound virtual memory system, explain how if a process modifies an arbitrary location in its virtual memory space, the change is not reflected at the same address of other processes. 3. In a paged virtual memory system, explain how if a process modifies an arbitrary location in its virtual memory space, the change is not reflected at the same address of other processes. 4. How does a base-and-bound virtual memory system prevent a process from accessing physical memory that is not allocated to the process? 5. How does a paged virtual memory system prevent a process from accessing physical memory that is not allocated to the process? 6. Explain the difference between internal and external fragmentation. 7. Does a base-and-bound virtual memory system have internal or external fragmentation? Explain your answer. 8. Does a paged virtual memory system have internal or external fragmentation? Explain your answer. 9. Give three benefits that a paged virtual memory system has over a base-and-bound virtual memory system. 10. Give four different circumstances under which a "page fault" can occur. 11. List the steps to process a page fault. 12. In a paged virtual memory system, why does the page size have to be a power of two? 13. List an advantage and a disadvantage of increasing the size of a page frame in a paged virtual memory system. 14. How does a paged virtual memory system distinguish between a process's user memory space and kernel memory space? 15. In a paged virtual memory system, can the computer's physical memory space be larger than a process's virtual memory space? Explain your answer. 16. In a paged virtual memory system, explain how two processes can share physical memory. 17. A page table entry (PTE) contains a page frame number (PFN) and additional meta-data about the page frame. Give three examples of meta-data bits that might be in a PTE. 18. In a paged virtual memory system with 32 bit virtual addresses and 8KB page frames, how many bits of a virtual address are used as an offset into a page frame and at most how many page frames can a process have allocated to it? 19 Consider a virtual address space of 64 pages of 1,024 bytes each, mapped onto a physical memory of 32 page frames. a.) How many bits are there is a virtual address? b.) How many bits are there in a physical address? 20 Consider a virtual address space of 32 pages with a 4KB page size, mapped onto a physical memory of 16 page frames. a.) How many bits are there is a virtual address? b.) How many bits are there in a physical address? 21. Define spatial reference locality. Define temporal reference locality. If a program does a linear search through a large array, is that an example with temporal or spatial locality? Explain why. (Hint: The answer depends on "spatial or temporal locality of what?", for example, memory references, TLB references, cache line references, or page references.) 22. Give two benefits that a demand paged virtual memory system has over a non-demand paged virtual memory system. 23. In a demand paged virtual memory system, what is the purpose of the allocation policy? What is the purpose of the replacement policy? 24. A demand paged virtual memory system must have a "fetch policy" that decides when a page should be loaded into primary memory. The simplest fetch policy is to load a page only when it has been page faulted. What is another possible fetch policy and what advantage might it have over the simplest one. (Hint: prefetch) 25. Assume that a computer has four pages in its virtual address space but only three physical pages frames. The following diagrams show two sequences of referenced virtual page numbers. Write down in the empty slots below each reference the pages that are loaded in the physical page frames at each page reference. Also, write down the total number of page hits and misses. Use the LRU page replacing policy in both cases. Page Referenced: 1 2 3 4 1 2 3 4 Page Frame 1: Page Frame 2: Page Frame 3: # of hits = # of misses = Page Referenced: 1 2 1 2 3 4 3 4 Page Frame 1: Page Frame 2: Page Frame 3: # of hits = # of misses = 26. Suppose a computer has 4 physical pages frames, and a process references its virtual pages (page numbers 0 through 7) in the following order: 0 2 1 3 5 4 6 3 7 4 7 3 3 5 5 3 1 1 1 7 2 3 4 1 a) Suppose the kernel uses FIFO page replacement algorithm. How many page faults would the process have? Which page references are page faults? b) Suppose the kernel uses LRU as the page replacement algorithm. Answer the above two questions. c) Suppose the kernel uses the optimal page replacement algorithm. Answer the above two questions. 27. Let w = 0,4,1,4,1,5,1,6,2,6,3,6,2,6,4,5 be a page reference stream. Given a static page frame allocation of 3 page frames and assuming the primary memory is initially unloaded, how many page faults will the given reference stream incur using the optimal strategy? Using the LRU strategy? 28. Consider the two-dimensional array int A[100][100]; where A[0][0] is at virtual address 200 in a paged memory system with pages of size 200 words and each int is one word. Suppose that this array is stored in "row major" form, which means that each row of 100 ints is stored in contiguous memory locations. (Notice that a column will not be stored contiguously.) The code for a small process that manipulates the matrix resides in page 0 (virtual addresses 0 to 199). Thus, every instruction fetch will be from page 0. Suppose that this process is allocated just three page frames. How many page faults are generated by the following array-initialization loops, using LRU replacement and assuming that page frame 0 already contains the process code and the other two page frames are initially empty? a.) for (int j = 0; j < 100; j++) for (int i = 0; i < 100; i++) A[i][j] = 0; b.) for (int i = 0; i < 100; i++) for (int j = 0; j < 100; j++) A[i][j] = 0